Signal Integrity Metrics
Parent topic: Signal Integrity Metrics

Board Delay on Rise

For a rising transition, the time interval between the switching threshold at the FPGA pin and the switching threshold at the far end of the board trace, in seconds. At the FPGA pin, the switching threshold is VMEAS. At the far end of the board trace, the switching threshold is the voltage halfway between steady-state VOL and steady-state VOH. VMEAS varies by device and I/O standard.

Note: For device-specific information about VMEAS, see the handbook for the target device, which is available from the Literature section of the Altera website.
Parent topic: Signal Integrity Metrics

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