Gate Level Simulation (Tools Menu)

This command only supports the Intel® Quartus® Prime Standard Edition. You access this command by pointing to Run Simulation Tool and clicking Gate Level Simulation on the Tools menu.
Note: The Gate Level Simulation command is available only after you have performed a full compilation on a project and you specify an EDA simulation tool. If you use this command after the design source files change, the EDA simulation tool runs the simulation with the data from the last compilation.

Allows you to perform an EDA gate level simulation from within the Intel® Quartus® Prime software without recompiling the design. The Intel® Quartus® Prime software launches the EDA simulation tool and processes the Intel® Quartus® Prime generated VHDL Output File (.vho) Definition,Verilog Output File (.vo) Definition, orSystemVerilog Output File (.svo) for the design.

If your design targets a supported device(Arria®, Cyclone® IV , and Stratix®) families, the EDA Gate Level Simulation list prompts you to select a timing model. The options appearing in the list indicate whether the timing model is fast or slow, the speed grade of the device, the voltage, and temperature. For example, selecting the Slow -2 1.1V 85 Model means you are selecting a slow model for a speed grade 2 device at 1.1 volts and 85 degrees C.