In a design, a reset signal that is generated in one clock domain and used in one or more other, asynchronous clock domains should follow the following guidelines:
- The reset signal should be synchronized with two or more cascading registers in the receiving asynchronous clock domain.
- The cascading registers should be triggered on the same clock edge.
- There should be no logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.
This rule is applied when the reset signal is synchronized but fails to adhere to the aforementioned guidelines.
The following image shows an example of an incorrectly synchronized reset signal. The reset signal in the receiving domain is only synchronized with one register; however, two cascaded registers are required to decrease the probability of metastability in the reset domain.
The following image shows example of an incorrectly synchronized reset signal. The cascaded registers in the receiving domain are triggered on different clock edges. When cascaded synchronization registers are triggered on different clock edges, the risk is higher that the second register will not have enough time to resolve the metastable output from the first register.
The following image shows example of an incorrectly synchronized reset signal. Logic exists between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain. The synchronizer may sample unintended data due to the glitches generated by combinational logic. Additionally, the extra toggling on the output of the combinatorial logic also increases the risk of metastability problems.
The following image shows an example of a correctly synchronized reset signal:
Synchronizing the reset signal delays the signal by an extra clock cycle; this delay should be considered when using the reset signal in a design.