In a design, the synchronization of an external reset (which is a primary input that is used as a reset signal) should follow the following guidelines:
- The external reset should be synchronized with two cascaded registers.
- The cascading registers should be triggered on the same clock edge.
This rule is applied when the external reset is synchronized but fails to adhere to the aforementioned guidelines.
The following image shows an example of an incorrectly synchronized external reset. The external reset is only synchronized with one register; however, two cascaded registers are required to decrease the probability of metastability in the reset domain.
The following image shows an example of an incorrectly synchronized external reset. The cascading registers are triggered on different clock edges. When the cascaded synchronization registers are triggered on different clock edges, the risk is higher that the second register will not have enough time to resolve the metastable output from the first register.
The following image shows an example of a correctly synchronized external reset:
