| Fitter Resources Reports | |
Reports the utilization of resources for each entity in the compilation hierarchy. The Compilation Hierarchy Node lists the names of the nodes in the design. For table entries with two numbers listed, the numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. The numbers in parentheses indicate the number of resources of the given type used by the node in that row.
Types of resources include Combinational Adaptive Look-Up Table (ALUT) Definition, Memory ALUTs, LUT_REGs,logic utilization of Adaptive Logic Module (ALM) Definition, dedicated logic registers, I/O registers, logic cell Definition, register Definition, block memory bits, memory bit DefinitionM512 memory blocks, M144K memory block Definition, M20k memory blocks, M4K memory blocks, M-RAM Definition,macrocell Definition,DSP block Definition, DSP block 9x9, 12x12 18x18, and 36x36 multipliers, virtual pins Definition, pins, carry chain logic cells, logic cells that only utilize the LUT in the logic cell, logic cells that only use the register, and logic cells that use both register and LUT, combinational with no register ALUT/register pair, register-only ALUT/register pair, combinational with a register ALUT/register pair, and the full hierarchy name. The specific resources listed in the report may vary depending on the device selected.
The Compilation Report list can contain multiple Resource Utilization by Entity reports, one generated during Analysis & Synthesis, partition based reports, and one generated during fitting. The Analysis & Synthesis Resources Reports show the resource usage of entities in the compilation hierarchy as calculated after logic synthesis, but before fitting. Because the Fitter's register packing Definition operation may reduce the number of logic cells in the design, the total usage reported in the Analysis & Synthesis Resource Utilization by Entity report might be greater than the total usage reported in the Fitter Resource Utilization by Entity report or the Fitter Resource Usage Reports.
The logic cell combinational count may be inaccurate if the inputs or outputs of an entity are not registered. Having unregistered inputs and outputs can cause logic to be optimized across entity boundaries, which means that logic that was originally in one entity may be named after logic in an adjacent entity and may thus be accounted towards the wrong entity.
The Fitter Resource Utilization by Entity report for Arria V, Cyclone V, and Stratix V device families describes logic utilization in terms of ALMs needed.
ALMs needed—calculated from the result of:
ALMs used in final placement – Estimate of ALMs recoverable by dense packing + Estimate of ALMs unavailable
ALMs used for memory—Lists the number of ALMs used to implement memory bits in core logic.
For more information on how the Quartus® Prime Standard Editionsoftware calculates logic utilization see the Fitter Resource Usage Summary report in this topic.