TimeQuest Multicorner Timing and Timing Model Datasheet Reports

Reports the results of timing analysis of both worst-case and best-case operating conditions for TimeQuest multicorner timing analysis and TimeQuest timing models to ensure the design meets timing across processes, voltage, and temperature (PVT).

Note:

The title of a report appears in red if that aspect of your design does not meet a specified requirement.

Setup Times Report:

Reports the setup times for clocks in the design subdivided by data port and clock port.

Data Port shows the names of the data port being analyzed.
Clock Port shows the clock port triggering the timing analysis.
Rise shows the amount of time in nanoseconds a rising edge must arrive at the data port before a clock edge, determined by the value in the Clock Edge column, arrives at the clock port.
Fall shows the amount of time in nanoseconds a falling edge must arrive at the data port before a clock edge, determined by the value in the Clock Edge column, arrives at the clock port.
Clock Edge shows the clock edge used in the Rise and Fall measurements.
Clock Reference shows the name of the clock. This can be different than the Clock Port name.

Hold Times Report:

Reports the hold times for clocks in the design in subdivided by data port and clock port.

Data Port shows the names of the data port being analyzed.
Clock Port shows the clock port triggering the timing analysis.
Rise shows the amount of time in nanoseconds a rising edge must arrive at the data port after a clock edge arrives at the clock port.
Fall shows the amount of time in nanoseconds a falling edge must arrive at the data port after a clock edge arrives at the clock port.
Clock Edge shows the clock edge used in the Rise and Fall measurements.
Clock Reference shows the name of the clock. This can be different than the Clock Port name.

Clock to Output Times Report:

Reports the clock to output times for clocks in the design in subdivided by data port and clock port.

Data Port shows the names of the data port being analyzed.
Clock Port shows the clock port triggering the timing analysis.
Rise shows the latest rise arrival time in nanoseconds that the clock at the clock port produces a change at the data port.
Fall shows the latest fall arrival time in nanoseconds that the clock at the clock port produces a change at the data port.
Clock Edge shows the clock edge used in the Rise and Fall measurements.
Clock Reference shows the name of the clock. This can differ from the Clock Port name.

Minimum Clock to Output Times Report:

Reports the minimum clock to output times for clocks in the design in subdivided by data port and clock port.

Data Port shows the names of the data port being analyzed.
Clock Port shows the clock port triggering the timing analysis.
Rise shows the earliest rise arrival time in nanoseconds that the clock at the clock port produces a change at the data port.
Fall shows the earliest fall arrival time in nanoseconds that the clock at the clock port produces a change at the data port.
Clock Edge shows the clock edge used in the Rise and Fall measurements.
Clock Reference shows the name of the clock. This can be different than the Clock Port name.

Propagation Delay Report:

Reports the longest delay in nanoseconds between the edges of a signal propagating from an input port to an output port.

Input Port shows the name of the input port being analyzed.
Output Port shows the name of the output port being analyzed.
RR shows the longest delay measured from rising edge to rising edge.
RF shows the longest delay measured from rising edge to falling edge.
FF shows the longest delay measured from falling edge to falling edge.
FR shows the longest delay measured from falling edge to rising edge.

Minimum Propagation Delay Report:

Reports the shortest delay in nanoseconds between the edges of a signal propagating from an input port to an output port.

Input Port shows the name of the input port being analyzed.
Output Port shows the name of the output port being analyzed.
RR shows the shortest delay measured from rising edge to rising edge.
RF shows the shortest delay measured from rising edge to falling edge.
FF shows the shortest delay measured from falling edge to falling edge.
FR shows the shortest delay measured from falling edge to rising edge.

Multicorner Timing Analysis Summary Report:

Reports a summary of the multicorner timing analysis separated into divisions for the Worst-case Slack and Design-wide TNS, or total negative slack, for clocks in the design. The values reported for each division include the names of all clocks, and the setup, hold, recovery, removal, and minimum pulse width for each clock.