| Keyboard Shortcuts and Toolbar Buttons | |
Command/Tool |
Shortcut |
|---|---|
Assignment Editor |
Ctrl+Shift + A, ![]() , or double-click an assignment annotation block |
Back-Annotate Assignments |
![]() |
Cascade |
Shift+F5 |
Close |
Ctrl+F4 or double-click the Document icon |
Change Manager |
Alt+6 |
Chip Planner |
|
Compilation Report |
Ctrl+R |
Copy |
Ctrl+C; ![]() ; Ctrl+Insert; or Press Ctrl+click, drag, and release |
Cut |
Ctrl+X, Shift+Del, or ![]() |
Delete |
Del |
Enter Port |
Double-click the symbol border or a port "x" to create or edit a port |
Insert Symbol |
Double-click a blank space in the Block Design File (.bdf) or Block Symbol File (.bsf) |
Exit the Quartus® Prime Standard Edition software |
Alt + F4 or double-click the Application icon |
Find |
Ctrl+F or ![]() |
Find Next |
F3 |
Fit in Window |
Ctrl+W or ![]() |
Flip Horizontal |
![]() |
Flip Vertical |
![]() |
Full Screen |
Ctrl+Alt+Space |
Hierarchy Down |
Ctrl+D or double-click a symbol or block |
Hierarchy Project Top |
Ctrl+T |
Hierarchy Up |
Ctrl+U |
Locate in Timing Closure Floorplan |
![]() |
Locate in Chip Planner |
![]() |
LogicLock Regions Window |
Alt+L or ![]() |
Message Locations |
Alt+4 or ![]() |
Messages window |
Alt+3 or ![]() |
New |
Ctrl+N or ![]() |
Node Finder |
Alt+2 or ![]() |
Open |
Ctrl+O or ![]() |
Paste |
Ctrl+V, Shift+Insert, or ![]() |
Ctrl+P or click ![]() to print the current file with the settings last specified in the Print dialog box |
|
Programmer |
![]() |
Project Navigator |
Alt+1 or ![]() |
Properties |
![]() |
Redo |
Ctrl+Y or ![]() |
Replace |
Ctrl+H |
Rotate by degrees (90, 180, 270) |
![]() |
RTL Viewer |
![]() |
Save |
Ctrl+S or ![]() |
Select All |
Ctrl+A |
Select a net |
Double-click a net |
Selection Tool |
Esc or ![]() |
Set as Top-Level Entity |
Ctrl+J |
Settings |
Ctrl+Shift+E |
Show Parameter Assignments |
![]() |
Show Pin and Location Assignments |
![]() |
SignalTap II Logic Analyzer |
![]() |
Simulation Report |
Ctrl+Shift+R |
Simulator Tool |
![]() |
Start Analysis & Elaboration |
![]() |
Start Analysis & Synthesis |
Ctrl+K or ![]() |
Start Assembler |
![]() |
Start Compilation |
Ctrl+L |
Start Compilation & Simulation |
Ctrl+Shift+K |
Start Design Assistant |
![]() |
Start Fitter |
![]() |
Start I/O Assignment Analysis |
![]() |
Start SignalProbe Compilation |
Ctrl+Shift+S |
Start Simulation |
Ctrl+I or ![]() |
Status windows |
Alt+5 or ![]() |
Stop Processing |
Ctrl+Shift+C |
Tcl console |
Alt+2 or ![]() |
Tile Horizontally |
Shift+F4 |
Timing Closure Floorplan |
![]() |
Undo |
Ctrl+Z, Alt+Backspace, ![]() |
Update Symbol or Block |
![]() |
Use Partial Line Selection |
![]() |
Zoom |
![]() |
Zoom In |
Ctrl+Space or ![]() |
Zoom Out |
Ctrl+Shift+Space or ![]() |