Report Spine Clock Utilization dialog box (Chip Planner)

Displays in the Chip Planner the spine clocks used by your design and the spine clocks reserved by the Fitter early in the compilation process.

• Report number of most utilized regions—Specifies the number of spine clock regions to report. The Spine Clock Utilization Report initially displays the most congested spine clock region. You can optionally display up to as many spine clock regions as you specify here.
• Report source clock regions—Displays the clock regions that feed each spine clock region.
• Report source nodes—Displays the source nodes for each clock region.
• Report clkctrl nodes—Displays theclock control node for each clock region.

The Fitter reserves spine clock resources early in the compilation process. To ensure that clocks can be routed to design resources during placement that occurs later in the compilation, the Fitter reserves a spine clock for every location a resource could be placed. Although unlikely, it is possible for the Fitter to reserve more spine clocks than are available in the device. If you see a high number of spine clocks reserved (but not used) in the Spine Clock Utilization Report, further development of your design might result in compilation failure.

You can reduce the number of spine clocks that the Fitter reserves with the following techniques:

• Use LogicLock regions to constrain the placement of logic in your design, and align boundaries of those LogicLock regions with clock region boundaries. (You can use the Clock Regions setting in the Layer Settings dialog box to display clock region boundaries in the Chip Planner.) Using LogicLock regions to constrain logic tells the Fitter that the logic can be placed only in that region; the Fitter reserves only spine clocks that route to that region--the LogicLock region reduces the number of spine clock resources reserved for the logic it contains.
• Reduce the number of clock resources required by your design by, for example, merging transceiver clocks.
• For devices with dual-regional clock networks, constrain logic to a regional clock region set and set the logic's global signal assignments to Regional instead of Dual-Regional.
• Demote some global clock signal assignments to a smaller clock region.
• Turn off automatic global signal promotion. In the Advanced Settings (Fitter) dialog box,turn off Auto Global Clock. But be aware that turning off Auto Global Clock makes resource placement more difficult, lengthens compilation time, degrades timing performance, and can cause compilation failure.