Example of Performing a Timing Simulation of a Synopsys VHDL Design with a Custom Megafunction Variation with the ModelSim Software

To perform a timing simulation on your Synopsys Synplify VHDL design using the ModelSim software after you compile your design in the Quartus^® Prime Standard Edition software, you can create a script that performs the following steps:

Compiles the <device family>_atoms.vhdand<device family>_components.vhd libraries.
Compiles the VHDL Output File (.vho) Definition that the Quartus^® Prime Standard Edition software generates during compilation. In this example, the VHDL Output File is plldesign.vho.
Compiles the testbench file. In this example, the testbench file name is plltest.vho.

Note:

Timing simulation for Stratix V devices is not supported in the Quartus^® Prime Standard Edition 10.1 release.

You can simulate the sample design in the ModelSim software by using the commands shown in the following sample script:

            
vlib work                                               # Create working directory
vcom /quartus/eda/sim_lib/apex20ke_atoms.vhd            # Read the simulation library 
vcom /quartus/eda/sim_lib/apex20ke_components.vhd       # Read the simulation library
                                                        # /quartus/ is the path to Quartus^® Prime Standard Edition
vmap apex20ke work                                      # Map the family name to work library
vcom plldesign.vho                                      # Compile the VHDL Output File
vcom plltest.vhd                                        # Compile the testbench file
vsim -t ps work.plltest(behave)                         # Simulate plltest with resolution in ps
add wave /plltest/*                                     # Add the port signals to the waveform view
run 1000 ns                                             # Run the