You can perform a functional simulation of the custom megafunction variation you created in Example of Creating a black box for a VHDL Custom Variation of a Megafunction with the Synplify Software before performing compilation in the Synopsys Synplify or the Quartus® Prime Standard Edition software.
To perform a functional simulation in the Modelsim software, you can create a script that performs the following steps:
Timing simulation for Stratix V devices is not supported in the Quartus® Prime Standard Edition 10.1 release.
You can simulate this sample design in the ModelSim software by using the commands shown in the following sample script:
vlib work # Create working directory
vcom /quartus/eda/sim_lib/altera_mf.vhd # Compile the altera_mf library
vcom /quartus/eda/sim_lib/altera_mf_components.vhd # Compile the altera_mf_components library
exec vmap altera_mf work # Create altera_mf library and map it to work
vcom my_pll.vhd # Compile generated megafunction file
vcom pll_design.vhd # Compile source instantiating module
vcom plltest.vhd # Compile the testbench file
vsim -t ps work.plltest(behave) # Simulate plltest with resolution in ps
add wave /plltest/* # Add the port signals to the waveform view
add wave /plltest/U0/U0/clock1 # Add the clock1 altclklock signal to the
# waveform view
run 1000 ns # Run the simulation for 1000 ns