To perform a functional simulation of a Verilog HDL design

If you have not already done so, perform Setting Up the VCS-MX Working Environment.
Create a .synopsys_vss.setup file to include the mapping information for the work library, and to direct the VCS MX software to use the functional simulation libraries during simulation:
```
WORK > <work library>  
220model > <work library>  
altera_mf > <work library>  
sgate > <work library>  
<work library> : <physical path to work library>
```
In the VCS MX shell, point the environment variable SYNOPSYS_SIM_SETUP to the .synopsys_vss.setup file.
To create a work library in the project directory, type the following command at a command prompt: mkdir <work library>
Note: Altera recommends using the Synopsys VCS MX default library names when you create a library. You should name the VCS MX software libraries as follows:
- When you run the VCS MX software independently from the Quartus^® Prime Standard Edition software, you should name your library work.
- When you run the VCS MX software automatically from the Quartus^® Prime Standard Edition software, the work library is named rtl_work for an RTL simulation or gate_work for a gate-level simulation. The library work is mapped to either rtl_work or gate_work.

To compile the Verilog Design File (.v) Definition, testbench file (if you are using one) and Altera simulation libraries, type the following commands at a command prompt:

vlogan /usr/quartus/eda/sim_lib/220model.v Enter
vlogan /usr/quartus/eda/sim_lib/altera_mf.v Enter
vlogan <design name>.v Enter
vlogan <test bench file>.v

If your design contains the alt2gbx IP Core, type the following commands to compile the appropriate libraries:

vlogan /usr/quartus/eda/sim_lib/sgate.v
vlogan /usr/quartus/eda/sim_lib/220model.v
vlogan /usr/quartus/eda/sim_lib/stratixiigx_hssi_atoms.v