Performing a Timing Simulation with the QuestaSim Software
Parent topic: Performing a Timing Simulation with the QuestaSim Software Previous topic: Performing a Timing Simulation with the QuestaSim Software Next topic: To perform a timing simulation with command-line commands

To perform a timing simulation with the QuestSim GUI

  1. If you have not already done so, compile libraries and design files with the QuestaSim software.
  2. If the design contains device-wide reset or device power-up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.
  3. On the Simulate menu, click Simulate. The Simulate dialog box appears.
  4. If you are simulating a Verilog HDL design, click the Verilog tab. Under Pulse Options, type 0 in the Error Limit and Rejection Limit boxes.
  5. If you are simulating a VHDL design, to specify the Standard Delay Format Output File (.sdo) Definition:
    1. Click the SDF tab.
    2. Click Add.
    3. In the Add SDF Entry dialog box, click Browse. The Select SDF File dialog box appears.
    4. In the Files of type list, select All Files (*.*).
    5. Select the Standard Delay Output File.
    6. Click Open.
    7. Click OK.
    Note: If you are using a testbench file to provide simulation stimuli to the design, in the Apply to region box, specify the path to the design instance in the testbench, starting from the top-level design file.
  6. Click the Design tab.
  7. In the Name list, expand the work directory and select the design entity that corresponds to the Standard Delay Output File.
  8. Click Add.
  9. Select the top-level Verilog HDL or VHDL Output File or testbench.
  10. Click Add.
  11. If you are simulating high-speed circuits (including designs that use HSSI, LVDS, or PLLs):
    1. Click the Other tab.
    2. In the Other options box, type +transport_int_delays and +transport_path_delays.
    3. Click OK.
  12. Click Load.
  13. To direct the QuestaSim software to generate a Value Change Dump File (.vcd) Definition that you can then use to perform power analysis in the Quartus® Prime Standard Edition PowerPlay Power Analyzer, type the following command at the QuestaSim prompt:
    source<testbench or design instance name>_dump_all_vcd_nodes.tcl

    The Tcl Script File (.tcl) Definition directs the QuestaSim software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.

  14. Perform the timing simulation in the QuestaSim software.
Related information

compile libraries and design files with the QuestaSim software
Setting Up Device-Wide Signals in Verilog HDL
Setting Up Device-Wide Signals in VHDL
Parent topic: Performing a Timing Simulation with the QuestaSim Software Previous topic: Performing a Timing Simulation with the QuestaSim Software Next topic: To perform a timing simulation with command-line commands

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