Performing a Timing Simulation with the ModelSim Software
Parent topic: Performing a Timing Simulation with the ModelSim Software Previous topic: Performing a Timing Simulation with the ModelSim Software Next topic: To perform a timing simulation with command-line commands

To perform a timing simulation with the ModelSim interface

  1. If you intend to use device-wide reset or power-on signals available in the Verilog Output File (.vo) Definition, VHDL Output File (.vho) Definition, or SystemVerilog Output File (.svo), if you have not already done so, ensure that these signals are driven appropriately during simulation.
  2. On the Simulate menu, click Simulate.
  3. If you are simulating a Verilog HDL design, click the Verilog tab. Under Pulse Options, type 0 in the Error Limit and Rejection Limit boxes.
  4. If you are simulating a VHDL design, to specify the Standard Delay Format Output File (.sdo) Definition:


    1. Click the SDF tab.
    2. Click Add.
    3. In the Add SDF Entry dialog box, click Browse. The Select SDF File dialog box appears.
    4. In the Files of type list, select All Files (*.*).
    5. Select the .sdo.
    6. Click Open.
    7. Click OK.
    Note: If you are using a testbench file to provide simulation stimuli to the design, in the Apply to region box, specify the path to the design instance in the testbench, starting from the top-level design file.
  5. Click the Design tab.
  6. In the Name list, expand the work directory and select the design entity that corresponds to the .sdo.
  7. Click Add.
  8. Select the top-level .vo, .svo, .vho, or testbench.
  9. Click Add.
  10. If you are simulating high-speed circuits (including designs that use HSSI, LVDS, or PLLs):
    1. Click the Other tab.
    2. In the Other options box type +transport_int_delays and +transport_path_delays.
    3. Click OK.
  11. Click Load.
  12. To direct the ModelSim software to generate a Value Change Dump File (.vcd) Definitionthat you can then use to perform power analysis in the Quartus® Prime Standard Edition PowerPlay Power Analyzer, type the following command at the ModelSim prompt:
    source<testbench or design instance name>_dump_all_vcd_nodes.tcl

    The Tcl Script File (.tcl) directs the ModelSim software to monitor and write the output signals contained in the Tcl Script File to a .vcd during simulation.

  13. Perform the timing simulation in the ModelSim software.
Note:

The EDA Netlist Writer generates a functional simulation netlist rather than a timing simulation netlist for designs that specify StratixV or newer device families, even if you specified a timing simulation netlist.

Parent topic: Performing a Timing Simulation with the ModelSim Software Previous topic: Performing a Timing Simulation with the ModelSim Software Next topic: To perform a timing simulation with command-line commands

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