Performing a Simulation of a Verilog HDL Design with the Active-HDL Software
Parent topic: Performing a Simulation of a Verilog HDL Design with the Active-HDL Software Previous topic: Perform a Post-Synthesis Simulation Next topic: Performing a Simulation of a VHDL Design with the Active-HDL Software

Perform a Gate-Level Simulation

  1. If you have not already done so, specify the settings to generate netlist files.
    1. To generate post-synthesis simulation netlist files:
      1. Perform Analysis and Synthesis. On the Processing menu, point to Start and click Start Analysis and Synthesis (you can also perform this after step 2).
      2. Turn on the Generate Netlist for Functional Simulation Only option by performing the following steps:
        1. On the Assignments menu, click EDA Tool Settings.
        2. In the Category list of the EDA Tool Settings page, click Simulation.
        3. In the Tool name list, select Active-HDL.
        4. Under EDA Netlist Writer settings, in the Format for output netlist list, select Verilog HDL. You can also modify where you want the post-synthesis netlist generated by editing or browsing to a directory in the Output directory box.
        5. Click More EDA Netlist Writer Settings. The More EDA Netlist Writer Settings dialog box appears. In the Existing options settings list, click Generate netlist for functional simulation only and select On from the Setting list under Options.
        6. Click OK.
        7. In the Settings dialog box, click OK.
      3. On the Processing menu, point to Start and click Start EDA Netlist Writer.
    2. To generate gate-level timing simulation netlist files:
      1. On the Assignments menu, click EDA Tool Settings.
      2. In the Category list of the EDA Tool Settings page, click Simulation.
      3. In the Tool name list, select Active-HDL.
      4. Under EDA Netlist Writer options, in the Format for output netlist list, select Verilog HDL. You can also modify where you want the post-synthesis netlist generated by editing or browsing to a directory in the Output directory box.
      5. Click OK.
      6. In the Settings dialog box, click OK.
      7. If you have not run a full compilation, perform a full compilation. On the Processing menu, click Start Compilation.
      8. If you have already run a full compilation, run the EDA Netlist Writer. On the Processing menu, point to Start and click Start EDA Netlist Writer.

      During the Full compilation or EDA Netlist Writer stage, the Quartus® Prime Standard Edition software produces a Verilog Output File (.vo) Definition and a Standard Delay Format Output File (.sdo) Definition used for gate-level timing simulations in the Active-HDL software. This netlist file is mapped to architecture-specific primitives. The timing information for the netlist is included in the Standard Delay Format Output File. The resulting netlist is located in the output directory you specified in the Settings dialog box, which defaults to <project directory>/simulation/activehdl.

      Note: The EDA Netlist Writer generates a functional simulation netlist rather than a timing simulation netlist for designs that specify the StratixV or newer device families, even if you specified a timing simulation netlist.
  2. To verify that pre-existing libraries are not attached in the Active-HDL software:
    1. On the View menu, click Library Manager. The Library Manager window appears.
    2. Browse to <Active-HDL installation directory>/vlib/altera_mf.
    3. If simulation libraries are present for your version of the Quartus® Prime Standard Editionsoftware, you can skip to step 5. Otherwise you can download the appropriate version library files from the Aldec website or create them manually with steps 3 and 4.
  3. To create a workspace in the Active-HDL software and compile simulation libraries:
    1. On the File menu, point to New and click Design. The New Design Wizard appears.
    2. Select Create an Empty Design and keep the Create New Workspace option selected.
    3. Click Next. The Property page appears. In the Property page, click Next.
    4. Type the name in the Design name and Library name fields, for example, stratix_ver. Select the location of your design in the Design folder field, and click Next. Altera recommends that you use same name for your design and the library.
    5. Click Finish to complete the wizard.
    6. On the Design menu, click Add files to Design.
    7. Browse to Quartus® Prime Standard Edition< installation directory>/eda/sim_lib and add the necessary simulation model files. For example, compile thestratixiii_atoms.vmodel files into thestratixiii_verlibrary.
    8. On the Design menu, clickCompile Allto compile all the files and add them to the design library, for example,stratixiii_atoms.v.
    9. On the File menu, clickClose Workspace.
  4. You must map the created library in the Active-HDL software. To register simulation libraries:
    1. On the View menu, clickLibrary Manager. The Library Manager window appears.
    2. On the Library menu, clickAttach Library.
    3. Locate the.libfile, for example,stratixiii.lib, from the design directory that you created in the previous steps and then clickOpen.
    4. To attach the simulation library as a global library inside your library manager and make it visible for any design in the Active-HDL software, turn onAttach as global library.
  5. To create a workspace in the Active-HDL software and compile your testbench and design files into the work library:
    1. On the File menu, point toNewand clickDesign. TheNew Design Wizardappears.
    2. SelectCreate an Empty Designand keep theCreate New Workspaceoption selected.
    3. ClickNext. ThePropertypage appears. In thePropertypage, clickNextto proceed to theDesign nameandLibrary namefields.
    4. Typeworkfor the design name and select the location of your design. Altera recommends that you use same name for your design and the library.
    5. ClickFinishto complete the wizard.
    6. On the Design menu, clickAdd files to Design.
    7. Browse to the Verilog HDL output file directory, for example,<project_directory>/simulation/activehdl, and add the Verilog Output File and Standard Delay Format Output File file.
    8. Browse to the testbench directory and add the testbench file.
    9. On the Design menu, clickCompile Allto compile the testbench and Verilog HDL output netlist files.
  6. To load a design in the Active-HDL software, in theDesign Browser, click theTop-level Selectionlist. Select the top-level module, which is your testbench with corresponding architecture.
  7. To initialize simulation in the Active-HDL software, on the Simulation menu, clickInitialize Simulation. This loads the simulation. TheDesign Browserautomatically switches to theStructuretab and displays the design tree.
  8. To perform the simulation in the Active-HDL software:
    1. On the File menu, point toNewand clickWaveform.
    2. Drag signals of interest from theStructuretab of theDesign Browserto theWaveformwindow.
    3. On the Simulation menu, clickRun Until.
    4. In the pop-up window, specify how long you want your simulation to run, for example, 500 ns.
Related information

Start Analysis and Synthesis
EDA Tool Settings
Simulation
EDA Netlist Writer settings
More EDA Netlist Writer Settings
Start EDA Netlist Writer
Start Compilation Command
Parent topic: Performing a Simulation of a Verilog HDL Design with the Active-HDL Software Previous topic: Perform a Post-Synthesis Simulation Next topic: Performing a Simulation of a VHDL Design with the Active-HDL Software

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