Allows you to turn on or off the option to compile test benches for Active-HDL, ModelSim, ModelSim-Altera, NC-Sim, VCS, and VCS MX.
- None— Turns off the test bench option. NativeLink compiles simulation models and design files.
- Compile test bench— Allows you to select a test bench that is compiled during simulation, if you created one or more test benches. NativeLink compiles simulation models, design files, testbench files, and starts simulation
 Scripting
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Keyword:eda_test_bench_enable_status Settings:not_used* | test_bench_mode | command_macro_mode *default |
- Test Benches— Opens the Test Benches dialog box, which allows you to create one or more test benches and specify settings for them.
- Use script to set up simulation— Allows you to specify a script file containing commands for the EDA simulation tool, for example:
- A ModelSim Macro File (.do) to perform a ModelSim simulation.
- A Tcl Script File (.tcl) Definition for NCSim (NC-Verilog or NC-VHDL).
- A file containing CLI commands for VCS.
- A file containing UCLI commands for VCS MX.
| Scripting
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Keyword:eda_nativelink_simulation_setup_script Settings:on | off* *default |
- Script to compile test bench— (ModelSim and ModelSim-Altera) Allows you to specify a ModelSim Macro File (.do) macro file to compile your test bench. NativeLink compiles the simulation models and design files. The script you provide is sourced after design files are compiled. Use this option when you want to create your own script to compile your testbench file and perform simulation.
| Scripting
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Keyword:eda_simulation_run_script Settings:<file name> |