More EDA Netlist Writer Settings Dialog Box
Parent topic: More EDA Netlist Writer Settings Dialog Box

Generate netlist for functional simulation only

Directs the Quartus® Prime Standard Edition software to generate a VHDL Output File (.vho) Definition,Verilog Output File (.vo) Definition, orSystemVerilog Output File (.svo) for functional simulation with other EDA simulation tools. A Standard Delay Format Output File (.sdo) Definition is not generated for the project. You can compile a VHDL Output File or Verilog Output File as part of performing a functional simulation with the all supported third-party simulation tools.

You can use this option if the design has finished compilation and you would like to check the functionality of your design implementation. A gate-level simulation without the timing component should run faster.

Scripting Information

Keyword:eda_generate_functional_netlist

Settings:on | off

*default
Related information

VHDL Output File(.vho)
Verilog Output File (.vo)
SystemVerilog Output File (.svo),
Standard Delay Format Output File (.sdo)
Scripting Information
Parent topic: More EDA Netlist Writer Settings Dialog Box

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